Vision AI-Based Circuit Simulation and Fault Finding: Trained model creation and Image classification

Abstract

This thesis evaluates an end-to-end, automated schematic-to-simulation pipeline that converts IEEE-standard electronic circuit diagrams into SPICE-compatible netlists and validated simulation outputs, thereby mitigating the inefficiency and error-prone nature of manual transcription in large-scale or time-critical workflows. Studies have established comprehensive foundation for the YOLOv11 based electronics detection pipeline. Neural networks and their deep variants have transformed computer vision aided with object detection frameworks. Specialised datasets for electronic circuits with combination of Neural detection models provides deep learning and automation opportunities. The proposed system comprises following tightly integrated stages: component detection using a YOLOv11 model trained on 19 device classes, Optical Character Recognition (OCR) to identify and mask textual regions prior to wire analysis, connectivity recovery via Hough Transform-based line extraction coupled with UnionFind graph construction; and circuit simulation in PySpice with scalar results overlaid directly on the source schematic. Empirical evaluation shows that the detector attains mAP of 0.5 of 92.4% with 93.1% precision and 91.7% recall, processing 1024×1024 schematics in 1.45 s to enable near real-time analysis. OCR masking reduces false wire detections by 26% and improves node assignment accuracy by 18%, yielding cleaner connectivity maps. The reconstruction module produces SPICE netlists with 92% structural correctness and 95% functional equivalence against manually curated references, while simulation validation indicates that 91% of generated netlists yield voltages and currents within ±5% of expected values. Results show an accurate, reliable, efficient schematic-to-simulation pipeline needing minimal intervention. It enables prototyping, design verification, reverse-engineering, and education, combining detection, OCR, graph reconstruction, and physics-based simulation to advance EDA.

Date of Award	2025
Original language	English
Supervisor	Gerald Zauner (Supervisor)