Abstract
Modern industrial applications increasingly utilize small, energy-efficient systems to perform complex tasks. These systems often combine microcontrollers and FPGA (FieldProgrammable Gate Array) components to achieve a high level of flexibility and performance. While microcontrollers are well-suited for programming complex processes, they
often reach their limits when faced with tasks that require high levels of parallelization
and specialized interfaces. In contrast, FPGAs offer an excellent solution to these challenges by implementing digital circuits directly as hardware, ensuring extremely high
parallelism and consistent timing.
The aim of this work is to evaluate typical digital bus interfaces of microcontrollers
and SOCs (Systems on Chip) and to select a suitable interface for an FPGA-based
slave implementation. This implementation is intended to enable efficient and fast data
transmission with minimal hardware effort, with a target transmission speed of approximately 1 Gbit/s. The interfaces are evaluated based on criteria such as transmission
speed, latency, PCB (Printed Circuit Board) implementation effort, FPGA slave implementation complexity and availability.
The RGMII (Reduced Gigabit Media Independent Interface) is chosen for the implementation as it meets the high data transmission requirements and provides an appropriate solution for connecting the FPGA to the Ethernet MAC (Media Access Controller). Another key factor in this decision is the lack of available IP cores (Intellectual
Property) that can directly facilitate data transmission from an Ethernet MAC, necessitating an in-house development. The developed implementation is comprehensively
verified using UVVM (Universal VHDL Verification Methodology) components to ensure its functionality in the simulated environment. This is followed by practical testing
on real hardware.
| Date of Award | 2024 |
|---|---|
| Original language | German (Austria) |
| Supervisor | Markus Pfaff (Supervisor) |