Implementation and Integration of an Avalon Streaming Verification Component for OSVVM

Abstract

This thesis explores advanced functional verification in digital hardware design, emphasizing the role of structured and automated methodologies in ensuring correctness and robustness. After outlining the theoretical foundations of verification and comparing established open-source frameworks, particular attention is given to the Open Source VHDL Verification Methodology (OSVVM). While OSVVM provides extensive infrastructure for randomized testing, logging, and coverage, it lacks protocol-specific Verification Components (VCs) for certain widely used interfaces. To address this gap, the thesis presents the design and implementation of a reusable VC for Intel’s Avalon Streaming protocol. The component follows OSVVM’s architectural conventions and supports key protocol features such as transaction-level modeling, backpressure, symbol ordering, and packet transfer. Through integration with OSVVM’s utilities, the VC enables advanced self-checking, randomization-based testing, and coverage-driven analysis. Beyond the concrete case of Avalon Streaming, the work provides a step-by-step guide for developing custom VCs within OSVVM. It thus serves both as a practical contribution to the OSVVM ecosystem and as a general methodology for extending verification frameworks to domain-specific protocols.

Date of Award	2025
Original language	English
Supervisor	Markus Pfaff (Supervisor)