Abstract
Due to technological advancements and the continuously increasing volume of network traffic, hardware solutions and high-throughput filtering methods are essential for processing network packets. The objective of this thesis was to implement a network analyzer capable of reading network packets via the Ethernet interface of a selected FPGA board and filtering them based on IP header values. However, during development,various limitations arose, significantly complicating the implementation of the Ethernet interface. As a result, a feasible alternative was chosen that could be implemented within the scope of this master’s thesis.
Firstly, the necessary toolchain for developing code for the chosen BittWare IA-420f FPGA board was set up. The FPGA board is controlled using Intel’s oneAPI programming interface and the C++ programming standard SYCL. oneAPI enables C++ code to be compiled for various hardware components, such as CPUs, GPUs, FPGAs, and other accelerators. The use of SYCL allowed for parallel programming of the system.
The network analyzer was implemented using both the BittWare IA-420f FPGA board and a CPU. Network packets from a PCAP file are filtered based on user-specified IP header values, and the matching packets are output to a new PCAP file. Performance evaluations revealed that the developed toolchain is capable of processing 1.2 Gb of network packet data per second.
Finally, a concept for integrating the network analyzer into a high-performance computing cluster was presented.
Date of Award | 2024 |
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Original language | German (Austria) |
Supervisor | Robert Kolmhofer (Supervisor) |