100Gbit/s Data Offloading from FPGAs using RoCEv2 RDMA and UDP

Abstract

This thesis evaluates the feasibility of using the RoCEv2 protocol to transfer a continuous data stream from an FPGA to a PC. Compared to standard network protocols, RoCEv2 transmissions are handled by the network card and require fewer CPU operations per transferred byte and reduces end-to-end latency. However, RoCEv2 is a complex protocol and is not designed for efficient implementation in FPGAs, so excessive resource usage is a concern. Additionally, fewer resources and open source projects use RoCEv2 than standard networking solutions, which makes designing a complete system with RoCEv2 difficult, so this project should also offer a starting point for future applications. A complete prototype system with a focus on the FPGA design was designed and implemented by using an open source RoCEv2 networking IP on the FPGA and adapting it to a streaming interface. The FPGA implementation can achieve a high throughput, but retransmissions in the RoCEv2 protocol are not handled correctly, which restricts the usability of the design in this thesis. However, a path to improving the design and implementing correct retransmissions is outlined in the thesis

Date of Award	2025
Original language	English
Supervisor	Markus Pfaff (Supervisor)