Transaction-Level State Charts in UML and SystemC with Zero-Time Evaluation

Rainer Leonhard Findenig, Thomas Leitner, Michael Velten, Wolfgang Ecker

Research output: Chapter in Book/Report/Conference proceedingsConference contributionpeer-review


UML State Charts provide an effective and intuitive means for the design entry of hardware systems. Several approaches exist to generate executable code in a variety of languages from UML State Charts, for hardware design most notably SystemC and Verilog. Since State Charts are especially interesting for designing virtual prototypes for early system simulation on the transaction level, this paper provides a methodology to allow the use of transactions inside State Charts and automatically generate executable SystemC code from them. Compared to previous approaches, our translation minimizes the amount of SystemC kernel interaction to improve the simulation performance. Based on a real-life and a best-case example we show that the speedup of code generated using the proposed approach compared to a conventional implementation averages around 2 to 30 while the generated code is still compatible with standard transaction-level models.
Original languageEnglish
Title of host publicationProceedings of DVCon 2010
Publication statusPublished - 2010
EventDesign & Verification Conference & Exhibition - San Jose, CA, United States
Duration: 24 Feb 201026 Feb 2010


ConferenceDesign & Verification Conference & Exhibition
Country/TerritoryUnited States
CitySan Jose, CA
Internet address


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