The Synthese of "Property Speficifation Language" (PSL) Assertions

Harlald Obereder, Markus Pfaff, Christian Saminger

Research output: Chapter in Book/Report/Conference proceedingsConference contribution

Abstract

In recent years more and more system designers discovered the impor-tance of Assertion Based Verification (ABV) in coverage driven, func-tional simulations to keep pace with ever-increasing complexity of mod-ern systems on chip (SoC). Using assertions plays a central role in the design-for-verification (DFV) methodology which is widely used in the industry. This paper presents a method that enables the major advan-tages of ABV beyond the borders of synthesis. By the use of the Prop-erty Specification Language (PSL) a way for the behavioral synthesis of properties will be shown. Furthermore the paper explains the integrated simulation of these hardware assertions by the aid of a hardware accel-erator and cosimulator. Overall, the presented approach can decrease the time to market while raising the quality for complex SoCs at the same time.
Translated title of the contributionThe Synthese of "Property Speficifation Language" (PSL) Assertions
Original languageGerman
Title of host publication1. Forschungsforum der österreichischen Fachhochschulen
Subtitle of host publicationTagungsband
Publication statusPublished - 2007
EventFirst Science Symposium of the Austrian Universities for Applied Sciences - Campus Urstein, Austria
Duration: 11 Apr 200712 Apr 2007

Conference

ConferenceFirst Science Symposium of the Austrian Universities for Applied Sciences
CountryAustria
CityCampus Urstein
Period11.04.200712.04.2007

Fingerprint Dive into the research topics of 'The Synthese of "Property Speficifation Language" (PSL) Assertions'. Together they form a unique fingerprint.

Cite this