State Chart Refinement Validation from Approximately Timed to Cycle Callable Models

Rainer Leonhard Findenig, Wolfgang Ecker

Research output: Chapter in Book/Report/Conference proceedingsConference contributionpeer-review

Abstract

Most of today's designs use a top-down design flow in which hardware is first implemented at transaction level and, as soon as it's functionality is verified, refined to a register transfer model which is conceptually a cycle true and cycle callable model. Traditionally, both the refinement and its validation are done by hand. We propose a design pattern for both the transaction-level and the cycle callable model that eases both steps: the refinement process is made more intuitive and verifying the cycle callable model is greatly simplified by automatically synchronizing the transaction-level model with the refined model.

Original languageEnglish
Title of host publication2010 International Symposium on System-on-Chip Proceedings, SoC 2010
Pages72-75
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 International Symposium on System-on-Chip - Tampere, Finland
Duration: 29 Sep 201030 Sep 2010

Publication series

Name2010 International Symposium on System-on-Chip Proceedings, SoC 2010

Conference

Conference2010 International Symposium on System-on-Chip
CountryFinland
CityTampere
Period29.09.201030.09.2010

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