TY - GEN
T1 - Single-Source Hardware Modeling of Different Abstraction Levels with State Charts
AU - Findenig, Rainer Leonhard
AU - Leitner, Thomas
AU - Ecker, Wolfgang
PY - 2012
Y1 - 2012
N2 - This paper presents an approach and a framework for hardware modeling on different abstraction levels, from untimed to cycle-accurate. Being based on UML State Charts, the graphical input language is intuitive to use and can directly serve as the documentation of the model. Compared to previous approaches, we propose an extension to UML that allows specifying all supported abstraction levels of a model in a single source, easing both development and debugging. We also present a code generator that allows selecting a specific abstraction level from the model to automatically generate SystemC code for it. Additionally, we use a modeling style extending existing work for purely cycle-accurate State Charts so that a previously presented code generation approach for VHDL can be reused.
AB - This paper presents an approach and a framework for hardware modeling on different abstraction levels, from untimed to cycle-accurate. Being based on UML State Charts, the graphical input language is intuitive to use and can directly serve as the documentation of the model. Compared to previous approaches, we propose an extension to UML that allows specifying all supported abstraction levels of a model in a single source, easing both development and debugging. We also present a code generator that allows selecting a specific abstraction level from the model to automatically generate SystemC code for it. Additionally, we use a modeling style extending existing work for purely cycle-accurate State Charts so that a previously presented code generation approach for VHDL can be reused.
UR - http://www.scopus.com/inward/record.url?scp=84874315967&partnerID=8YFLogxK
U2 - 10.1109/HLDVT.2012.6418241
DO - 10.1109/HLDVT.2012.6418241
M3 - Conference contribution
SN - 9781467328975
T3 - Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
SP - 41
EP - 48
BT - 2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012
T2 - High Level Design Validation and Test Workshop (HLDVT) 2012
Y2 - 9 November 2012 through 10 November 2012
ER -