Single-Source Hardware Modeling of Different Abstraction Levels with State Charts

Rainer Leonhard Findenig, Thomas Leitner, Wolfgang Ecker

Research output: Chapter in Book/Report/Conference proceedingsConference contributionpeer-review

1 Citation (Scopus)

Abstract

This paper presents an approach and a framework for hardware modeling on different abstraction levels, from untimed to cycle-accurate. Being based on UML State Charts, the graphical input language is intuitive to use and can directly serve as the documentation of the model. Compared to previous approaches, we propose an extension to UML that allows specifying all supported abstraction levels of a model in a single source, easing both development and debugging. We also present a code generator that allows selecting a specific abstraction level from the model to automatically generate SystemC code for it. Additionally, we use a modeling style extending existing work for purely cycle-accurate State Charts so that a previously presented code generation approach for VHDL can be reused.

Original languageEnglish
Title of host publication2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012
Pages41-48
Number of pages8
DOIs
Publication statusPublished - 2012
EventHigh Level Design Validation and Test Workshop (HLDVT) 2012 - Huntington Beach, United States
Duration: 9 Nov 201210 Nov 2012

Publication series

NameProceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
ISSN (Print)1552-6674

Conference

ConferenceHigh Level Design Validation and Test Workshop (HLDVT) 2012
CountryUnited States
CityHuntington Beach
Period09.11.201210.11.2012

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