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Optimizing the Hardware Usage of Parallel FSMs
Rainer Leonhard Findenig
,
Florian Eibensteiner
,
Markus Pfaff
R&D-Headquarters
Research Center Hagenberg
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Keyphrases
Finite State Machine
100%
Operating Frequency
75%
Cutout
25%
Hardware Design
25%
Chip Area
25%
Operating System
25%
Scheduling Mechanism
25%
Low Speed
25%
Clock Domain
25%
Hardware Resources
25%
Processor Frequency
25%
Chip-based
25%
Single Clock
25%
Computer Science
Finite-State Machine
100%
Operating Frequency
75%
Hardware Design
25%
System on a Chip
25%
Hardware Resource
25%
Scheduling Mechanism
25%
Operating System
25%
Engineering
Finite-State Machine
100%
Operating Frequency
75%
Chip Area
25%
Additional Cost
25%