Optimizing the Hardware Usage of Parallel FSMs

Rainer Leonhard Findenig, Florian Eibensteiner, Markus Pfaff

Research output: Chapter in Book/Report/Conference proceedingsConference contribution

Abstract

Hardware design is traditionally done by modeling finite state machines (FSMs). In this paper, we present how a basic round-robing scheduling mechanism, well-known from operating systems, can be applied to a design that needs several identical FSMs running (quasi) in parallel. This approach allows exploiting the classical trade-off between chip area and operating frequency to severely cut down the hardware resources needed to implement the FSMs by increasing the operating frequency of the design. We additionally show that, in a system-on-a-chip design using only a single clock domain, the design's overall operating frequency is dependent on the processor's frequency, making especially low-speed communication cores already clocked faster than needed. This means that with regard to the design's frequency, our approach may come at no additional cost.
Original languageEnglish
Title of host publicationComputer Aided Systems Theory, EUROCAST 2009 - 12th International Conference, Revised Selected Papers
Pages63-68
Number of pages6
DOIs
Publication statusPublished - 2009
EventTwelve International Conference on Computer Aided Systems Theory 2009 - Las Palmas, Spain
Duration: 15 Feb 200920 Feb 2009
http://www.iuctc.ulpgc.es/spain/eurocast2009/index.html

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume5717 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

ConferenceTwelve International Conference on Computer Aided Systems Theory 2009
CountrySpain
CityLas Palmas
Period15.02.200920.02.2009
Internet address

Keywords

  • FSM
  • Resource sharing
  • Scheduling
  • Serialization

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