TY - GEN
T1 - Hardware-software co-simulation environment for a multiplier free blocker detection approach for LTE systems
AU - Sravanthi, Vajje
AU - Schlechter, Thomas
PY - 2011
Y1 - 2011
N2 - For mobile user equipments (UE) a careful power management is essential. Despite this fact, quite an amount of energy is wasted in todays UEs analog and digital frontends. Those are engineered for extracting the wanted signal from a spectral environment defined in the corresponding communication standards with their extremely tough requirements. In a real receiving process those requirements can typically be considered as dramatically less critical. Knowledge about the actual environmental spectral conditions allows to reconfigure both frontends to the actual needs and to save energy. In the recent past several approaches solving this issue for Long Term Evolution systems using multiplier free multi rate low cost filter banks have been discussed. In this paper we present a co-simulation environment for an efficient hardware implementation of the proposed algorithms using Matlab and two Field Programmable Gate Array platforms. The specific hardware setup as well as the used communication protocols between hardware and software are discussed.
AB - For mobile user equipments (UE) a careful power management is essential. Despite this fact, quite an amount of energy is wasted in todays UEs analog and digital frontends. Those are engineered for extracting the wanted signal from a spectral environment defined in the corresponding communication standards with their extremely tough requirements. In a real receiving process those requirements can typically be considered as dramatically less critical. Knowledge about the actual environmental spectral conditions allows to reconfigure both frontends to the actual needs and to save energy. In the recent past several approaches solving this issue for Long Term Evolution systems using multiplier free multi rate low cost filter banks have been discussed. In this paper we present a co-simulation environment for an efficient hardware implementation of the proposed algorithms using Matlab and two Field Programmable Gate Array platforms. The specific hardware setup as well as the used communication protocols between hardware and software are discussed.
UR - http://www.scopus.com/inward/record.url?scp=80053639835&partnerID=8YFLogxK
U2 - 10.1109/INDS.2011.6024837
DO - 10.1109/INDS.2011.6024837
M3 - Conference contribution
AN - SCOPUS:80053639835
SN - 9781457707599
T3 - Proceedings of the Joint 3rd International Workshop on Nonlinear Dynamics and Synchronization, INDS'11 and 16th International Symposium on Theoretical Electrical Engineering, ISTET'11
SP - 356
EP - 361
BT - Proceedings of the Joint 3rd International Workshop on Nonlinear Dynamics and Synchronization, INDS'11 and 16th International Symposium on Theoretical Electrical Engineering, ISTET'11
T2 - Joint 3rd International Workshop on Nonlinear Dynamics and Synchronization, INDS'11 and 16th International Symposium on Theoretical Electrical Engineering, ISTET'11
Y2 - 25 July 2011 through 27 July 2011
ER -