Abstract
In recent years more and more system designers discovered the impor-tance of Assertion Based Verification (ABV) in coverage driven, func-tional simulations to keep pace with ever-increasing complexity of mod-ern systems on chip (SoC). Using assertions plays a central role in the design-for-verification (DFV) methodology which is widely used in the industry. This paper presents a method that enables the major advan-tages of ABV beyond the borders of synthesis. By the use of the Prop-erty Specification Language (PSL) a way for the behavioral synthesis of properties will be shown. Furthermore the paper explains the integrated simulation of these hardware assertions by the aid of a hardware accel-erator and cosimulator. Overall, the presented approach can decrease the time to market while raising the quality for complex SoCs at the same time.
| Translated title of the contribution | The Synthese of "Property Speficifation Language" (PSL) Assertions |
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| Original language | German |
| Title of host publication | 1. Forschungsforum der österreichischen Fachhochschulen |
| Subtitle of host publication | Tagungsband |
| Publication status | Published - 2007 |
| Event | First Science Symposium of the Austrian Universities for Applied Sciences - Campus Urstein, Austria Duration: 11 Apr 2007 → 12 Apr 2007 |
Conference
| Conference | First Science Symposium of the Austrian Universities for Applied Sciences |
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| Country/Territory | Austria |
| City | Campus Urstein |
| Period | 11.04.2007 → 12.04.2007 |