Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis

Translated title of the contribution: Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis

Rainer Leonhard Findenig, Thomas Leitner, Volkan Esen, Wolfgang Ecker

Research output: Chapter in Book/Report/Conference proceedings › Conference contribution › peer-review

Translated title of the contribution	Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis
Original language	German
Title of host publication	Proceedings of DVCon 2011
Publication status	Published - 2011
Event	Design & Verification Conference & Exhibition - San Jose, CA, United States Duration: 28 Feb 2011 → 3 Mar 2011

Conference	Design & Verification Conference & Exhibition
Country/Territory	United States
City	San Jose, CA
Period	28.02.2011 → 03.03.2011

Cite this

@inproceedings{c5dd3c5782dd430bb0841c120bf88a85,

title = "Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis",

author = "Findenig, {Rainer Leonhard} and Thomas Leitner and Volkan Esen and Wolfgang Ecker",

year = "2011",

language = "Deutsch",

booktitle = "Proceedings of DVCon 2011",

note = "Design & Verification Conference & Exhibition ; Conference date: 28-02-2011 Through 03-03-2011",

}

TY - GEN

T1 - Consistent SystemC and VHDL Code Generation from State Charts for Virtual Prototyping and RTL Synthesis

AU - Findenig, Rainer Leonhard

AU - Leitner, Thomas

AU - Esen, Volkan

AU - Ecker, Wolfgang

PY - 2011

Y1 - 2011

UR - https://pdfs.semanticscholar.org/def7/f456155c506d24dabf04b64b03e12513f92e.pdf

M3 - Konferenzbeitrag

BT - Proceedings of DVCon 2011

T2 - Design & Verification Conference & Exhibition

Y2 - 28 February 2011 through 3 March 2011

ER -