Complexity Estimates of a SHA-1 Near-Collision Attack for GPU and FPGA

Jürgen Fuß, Stefan Gradinger, Bernhard Greslehner-Nimmervoll, Robert Kolmhofer

Research output: Chapter in Book/Report/Conference proceedingsConference contributionpeer-review

2 Citations (Scopus)

Abstract

The complexity estimate of a hash collision algorithm is given by the unit hash compressions. This paper shows that this figure can lead to false runtime estimates when accelerating the algorithm by the use of graphics processing units (GPU) and field-programmable gate arrays (FPGA). For demonstration, parts of the CPU reference implementation of Marc Stevens' SHA-1 Near-Collision Attack are implemented on these two accelerators by taking advantage of their specific architectures. The implementation, runtime behavior and performance of these ported algorithms are discussed, and in conclusion, it is shown that the acceleration results in different complexity estimates for each type of coprocessor.
Original languageEnglish
Title of host publicationProceedings - 10th International Conference on Availability, Reliability and Security, ARES 2015
PublisherIEEE
Pages274-280
Number of pages7
ISBN (Electronic)9781467365901
DOIs
Publication statusPublished - 16 Oct 2015
Event10th International Conference on Availability, Reliability and Security (ARES), 2015 - Toulouse, France
Duration: 24 Aug 201527 Aug 2015

Publication series

NameProceedings - 10th International Conference on Availability, Reliability and Security, ARES 2015

Conference

Conference10th International Conference on Availability, Reliability and Security (ARES), 2015
CountryFrance
CityToulouse
Period24.08.201527.08.2015

Keywords

  • SHA-1
  • near-collision
  • GPU
  • FPGA
  • high-performance computing
  • Hash collisions
  • Hash function
  • Near-collision

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