An innovative approach to the design of medium voltage power electronics printed circuit-boards

Going towards maximization of power density and dynamics, the supply of electrical and electronics components in industrial, electrified transportation and renewable electrical assets is shifting from sinusoidal AC to modulated AC and DC, involving voltage and load transients. Voltage is increasing to the MV range so that power electronics boards must be designed to withstand, for the specified operation life, high electric fields and temperatures. Very fast switching time and high modulation and carrier frequencies have to be also managed. This determines electrical, thermal and mechanical stress profiles which can change significantly with supply voltage and time. They can affect (increasing) electrothermal and mechanical aging rate regarding both intrinsic and extrinsic aging factors. As an example, the electric field in bulk insulation defects or on the PCB surface can incept partial discharges, PD, for some stress conditions, with different PD amplitude and repetition rate from AC to DC. This impacts on extrinsic aging rate, so that life reduction can be dramatic even if PD activity would be discontinuous. This paper introduces an innovative approach to power electronic board design which should allow an optimized design of PCB insulation systems as regards their reliability, life, shape and dimensions/weight, taking into account the risk of generating extrinsic aging phenomena. The so called “three-leg approach” is based on the comparison and match of results coming from electric stress profile simulation, discharge modelling and partial discharge, PD, measurements under the type of waveform that a PCB can experience, specifically modulated AC and DC. It consists of extracting the information of maximum bulk and surface (tangential) electrical stress (field) at operating temperatures, comparing them with models for partial discharge inception that associated the stress to PD likelihood and linking such results with PD measurements (particularly the partial discharge inception voltage, PDIV). This would provide a PD-free design allowing inference on connector technology and shape, as well as quantities as creepage and clearance. The focus in this paper is describing how to deal with the first leg approach on a 5 kV PCB, showing electric field simulation results and explaining how discharge modelling and PD measurement will complete the whole optimized design.