Today's hardware designs increasingly use transaction-level modeling to allow both easier hardware architecture evaluation and earlier software development. Such models are mostly based on an abstract representation of the system and communication and the system's timing is only approximated or even completely omitted. Few methods are available, though, to assist the designers during the refinement from the transaction-level model to a cycle-callable model that is implementable in hardware. Previous work has been done to allow synchronized cosimulation between the two models, where the cycle-callable model's timing is used to drive the transaction-level model, which is in turn used to verify the cycle-callable model's state transitions. This work presents a SystemC design pattern to achieve such a cosimulation. Experimental results show that the simulation overhead introduced by the cosimulation is negligible.
|Title of host publication
|Proceedings Austrochip 2009
|Published - 2009
|Austrochip 2009 - Graz, Austria
Duration: 7 Oct 2009 → 7 Oct 2009
|07.10.2009 → 07.10.2009