MIEC operation code generator for the RISC-V platform

Activity: Other


This project focuses on the development of an operation code generator. This is intended to generate the appropriate RISC V machine code from the MIEC intermediate language (three-address code) and store it in an executable file. A virtual machine is required for execution on Windows to enable calculations and output on the console. The work steps include a detailed analysis of the existing system, development and implementation of the RISC V-OpCode generator, special attention to the application interface, integration into the existing compiler architecture, development of a virtual machine for executing the RISC V code and corresponding tests of the generator.
Period1 Oct 202230 Jun 2023
Degree of RecognitionRegional