State Chart Refinement Validation from Approximately Timed to Cycle Callable Models

Rainer Leonhard Findenig, Wolfgang Ecker

Publikation: Beitrag in Buch/Bericht/TagungsbandKonferenzbeitragBegutachtung

Abstract

Most of today's designs use a top-down design flow in which hardware is first implemented at transaction level and, as soon as it's functionality is verified, refined to a register transfer model which is conceptually a cycle true and cycle callable model. Traditionally, both the refinement and its validation are done by hand. We propose a design pattern for both the transaction-level and the cycle callable model that eases both steps: the refinement process is made more intuitive and verifying the cycle callable model is greatly simplified by automatically synchronizing the transaction-level model with the refined model.

OriginalspracheEnglisch
Titel2010 International Symposium on System-on-Chip Proceedings, SoC 2010
Seiten72-75
Seitenumfang4
DOIs
PublikationsstatusVeröffentlicht - 2010
Veranstaltung2010 International Symposium on System-on-Chip - Tampere, Finnland
Dauer: 29 Sep. 201030 Sep. 2010

Publikationsreihe

Name2010 International Symposium on System-on-Chip Proceedings, SoC 2010

Konferenz

Konferenz2010 International Symposium on System-on-Chip
Land/GebietFinnland
OrtTampere
Zeitraum29.09.201030.09.2010

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