TY - GEN
T1 - State Chart Refinement Validation from Approximately Timed to Cycle Callable Models
AU - Findenig, Rainer Leonhard
AU - Ecker, Wolfgang
PY - 2010
Y1 - 2010
N2 - Most of today's designs use a top-down design flow in which hardware is first implemented at transaction level and, as soon as it's functionality is verified, refined to a register transfer model which is conceptually a cycle true and cycle callable model. Traditionally, both the refinement and its validation are done by hand. We propose a design pattern for both the transaction-level and the cycle callable model that eases both steps: the refinement process is made more intuitive and verifying the cycle callable model is greatly simplified by automatically synchronizing the transaction-level model with the refined model.
AB - Most of today's designs use a top-down design flow in which hardware is first implemented at transaction level and, as soon as it's functionality is verified, refined to a register transfer model which is conceptually a cycle true and cycle callable model. Traditionally, both the refinement and its validation are done by hand. We propose a design pattern for both the transaction-level and the cycle callable model that eases both steps: the refinement process is made more intuitive and verifying the cycle callable model is greatly simplified by automatically synchronizing the transaction-level model with the refined model.
UR - http://www.scopus.com/inward/record.url?scp=78650197951&partnerID=8YFLogxK
U2 - 10.1109/ISSOC.2010.5625551
DO - 10.1109/ISSOC.2010.5625551
M3 - Conference contribution
SN - 9781424482764
T3 - 2010 International Symposium on System-on-Chip Proceedings, SoC 2010
SP - 72
EP - 75
BT - 2010 International Symposium on System-on-Chip Proceedings, SoC 2010
T2 - 2010 International Symposium on System-on-Chip
Y2 - 29 September 2010 through 30 September 2010
ER -