Optimizing the Hardware Usage of Parallel FSMs

Rainer Leonhard Findenig, Florian Eibensteiner, Markus Pfaff

Publikation: Beitrag in Buch/Bericht/TagungsbandKonferenzbeitrag

Abstract

Hardware design is traditionally done by modeling finite state machines (FSMs). In this paper, we present how a basic round-robing scheduling mechanism, well-known from operating systems, can be applied to a design that needs several identical FSMs running (quasi) in parallel. This approach allows exploiting the classical trade-off between chip area and operating frequency to severely cut down the hardware resources needed to implement the FSMs by increasing the operating frequency of the design. We additionally show that, in a system-on-a-chip design using only a single clock domain, the design's overall operating frequency is dependent on the processor's frequency, making especially low-speed communication cores already clocked faster than needed. This means that with regard to the design's frequency, our approach may come at no additional cost.
OriginalspracheEnglisch
TitelComputer Aided Systems Theory, EUROCAST 2009 - 12th International Conference, Revised Selected Papers
Seiten63-68
Seitenumfang6
DOIs
PublikationsstatusVeröffentlicht - 2009
VeranstaltungTwelve International Conference on Computer Aided Systems Theory 2009 - Las Palmas, Spanien
Dauer: 15 Feb 200920 Feb 2009
http://www.iuctc.ulpgc.es/spain/eurocast2009/index.html

Publikationsreihe

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Band5717 LNCS
ISSN (Print)0302-9743
ISSN (elektronisch)1611-3349

Konferenz

KonferenzTwelve International Conference on Computer Aided Systems Theory 2009
Land/GebietSpanien
OrtLas Palmas
Zeitraum15.02.200920.02.2009
Internetadresse

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