Die Synthese von "Property Specification Language" (PSL) Assertions

In recent years more and more system designers discovered the impor-tance of Assertion Based Verification (ABV) in coverage driven, func-tional simulations to keep pace with ever-increasing complexity of mod-ern systems on chip (SoC). Using assertions plays a central role in the design-for-verification (DFV) methodology which is widely used in the industry. This paper presents a method that enables the major advan-tages of ABV beyond the borders of synthesis. By the use of the Prop-erty Specification Language (PSL) a way for the behavioral synthesis of properties will be shown. Furthermore the paper explains the integrated simulation of these hardware assertions by the aid of a hardware accel-erator and cosimulator. Overall, the presented approach can decrease the time to market while raising the quality for complex SoCs at the same time.