The complexity estimate of a hash collision algorithm is given by the unit hash compressions. This paper shows that this figure can lead to false runtime estimates when accelerating the algorithm by the use of graphics processing units (GPU) and field-programmable gate arrays (FPGA). For demonstration, parts of the CPU reference implementation of Marc Stevens' SHA-1 Near-Collision Attack are implemented on these two accelerators by taking advantage of their specific architectures. The implementation, runtime behavior and performance of these ported algorithms are discussed, and in conclusion, it is shown that the acceleration results in different complexity estimates for each type of coprocessor.
|Name||Proceedings - 10th International Conference on Availability, Reliability and Security, ARES 2015|
|Konferenz||10th International Conference on Availability, Reliability and Security (ARES), 2015|
|Zeitraum||24.08.2015 → 27.08.2015|
- high-performance computing