Complexity Estimates of a SHA-1 Near-Collision Attack for GPU and FPGA

Jürgen Fuß, Stefan Gradinger, Bernhard Greslehner-Nimmervoll, Robert Kolmhofer

Publikation: Beitrag in Buch/Bericht/TagungsbandKonferenzbeitragBegutachtung

2 Zitate (Scopus)

Abstract

The complexity estimate of a hash collision algorithm is given by the unit hash compressions. This paper shows that this figure can lead to false runtime estimates when accelerating the algorithm by the use of graphics processing units (GPU) and field-programmable gate arrays (FPGA). For demonstration, parts of the CPU reference implementation of Marc Stevens' SHA-1 Near-Collision Attack are implemented on these two accelerators by taking advantage of their specific architectures. The implementation, runtime behavior and performance of these ported algorithms are discussed, and in conclusion, it is shown that the acceleration results in different complexity estimates for each type of coprocessor.
OriginalspracheEnglisch
TitelProceedings - 10th International Conference on Availability, Reliability and Security, ARES 2015
Herausgeber (Verlag)IEEE
Seiten274-280
Seitenumfang7
ISBN (elektronisch)9781467365901
DOIs
PublikationsstatusVeröffentlicht - 16 Okt 2015
Veranstaltung10th International Conference on Availability, Reliability and Security (ARES), 2015 - Toulouse, Frankreich
Dauer: 24 Aug 201527 Aug 2015

Publikationsreihe

NameProceedings - 10th International Conference on Availability, Reliability and Security, ARES 2015

Konferenz

Konferenz10th International Conference on Availability, Reliability and Security (ARES), 2015
Land/GebietFrankreich
OrtToulouse
Zeitraum24.08.201527.08.2015

Schlagwörter

  • SHA-1
  • near-collision
  • GPU
  • FPGA
  • high-performance computing

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