Behavioral synthesis of property specification language (PSL) assertions

Harlald Obereder, Markus Pfaff, Christian Saminger

Publikation: Beitrag in Buch/Bericht/TagungsbandKonferenzbeitragBegutachtung

2 Zitate (Scopus)

Abstract

In recent years more and more system designers discovered the importance of Assertion Based Verification (ABV) in coverage driven, functional simulations to keep pace with ever-increasing complexity of modern systems on chip (SoC). Using assertions plays a central role in the design-for-verification (DFV) methodology which is widely used in the industry. This paper presents a method that enables the major advantages of ABV beyond the borders of synthesis. By the use of the Property Specification Language (PSL) a way for the behavioral synthesis of properties will be shown. Furthermore the paper explains the integrated simulation of these hardware assertions by the aid of a hardware accelerator and cosimulator. Overall, the presented approach can decrease the time to market while raising the quality for complex SoCs at the same time.

OriginalspracheEnglisch
Titel18th IEEE/IFIP International Workshop on Rapid System Prototyping, RSP '07, Proceedings
Seiten157-160
Seitenumfang4
DOIs
PublikationsstatusVeröffentlicht - 2007
Veranstaltung18th IEEE/IFIP International Workshop on Rapid System Prototyping, RSP '07 - Porto alegre, Brasilien
Dauer: 28 Mai 200730 Mai 2007

Publikationsreihe

NameProceedings of the International Workshop on Rapid System Prototyping
ISSN (Print)1074-6005

Konferenz

Konferenz18th IEEE/IFIP International Workshop on Rapid System Prototyping, RSP '07
Land/GebietBrasilien
OrtPorto alegre
Zeitraum28.05.200730.05.2007

Schlagwörter

  • PSL
  • Property Specification Language
  • Synthesis
  • Assertion

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